Implantable stimulation devices are devices that generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder sublaxation, etc. The present invention may find applicability in all such applications, although the description that follows will generally focus on the use of the invention within a spinal cord stimulation system, such as that disclosed in U.S. Pat. No. 6,516,227 (“the '227 patent”), issued Feb. 4, 2003 in the name of inventors Paul Meadows et al., which is incorporated herein by reference in its entirety.
Spinal cord stimulation is a well-accepted clinical method for reducing pain in certain populations of patients. A Spinal Cord Stimulation (SCS) system typically includes an Implantable Pulse Generator (IPG) or Radio-Frequency (RF) transmitter and receiver, electrodes, at least one electrode lead, and, optionally, at least one electrode lead extension. The electrodes, which reside on a distal end of the electrode lead, are typically implanted along the dura of the spinal cord, and the IPG or RF transmitter generates electrical pulses that are delivered through the electrodes to the nerve fibers within the spinal column. Individual electrode contacts (the “electrodes”) are arranged in a desired pattern and spacing to create an electrode array. Individual wires within one or more electrode leads connect with each electrode in the array. The electrode lead(s) exit the spinal column and generally attach to one or more electrode lead extensions. The electrode lead extensions, in turn, are typically tunneled around the torso of the patient to a subcutaneous pocket where the IPG or RF receiver is implanted. Alternatively, the electrode lead may directly connect with the IPG or RF receiver. For examples of other SCS systems and other stimulation system, see U.S. Pat. Nos. 3,646,940 and 3,822,708, which are hereby incorporated by reference in their entireties. Of course, implantable pulse generators are active devices requiring energy for operation, such as is provided by an implanted battery or an external power source.
An IPG may include one or more output current sources/sinks that are configured to supply/receive stimulating current to/from the electrodes on the IPG, and ultimately to/from tissue. For example, FIG. 1 shows an exemplary output current source 500 and a corresponding output current sink 501 used to stimulate tissue, exemplified generically as a load 505 (R). As one skilled in the art will understand, transistors M1 and M3 in the output current source 500, and transistors M2 and M4 in the output current sink, comprise a current mirror. However, other current source or sink circuitry can be used, such as that disclosed in U.S. Pat. No. 7,539,538, which is incorporated herein by reference in its entirety.
Both the source 500 and sink 501 are coupled to a current generator 506 configured to generate a reference current, Iref. A suitable current generator is disclosed in U.S. Pat. No. 6,181,969 (“the '969 patent”), issued Jan. 30, 2001 in the name of inventor John C. Gord, which is incorporated herein by reference in its entirety. The reference current in both the output current source/sink 500/501 is input into a digital-to-analog converter (DAC) configured to regulate the current that is delivered to the load 505. Thus, source 500 employs DAC circuitry 502, while sink 501 employs DAC circuitry 503, which circuit is illustrated only generically here but is fully disclosed in the above-incorporated '969 patent.
DAC circuitry 502, 503 is configured to regulate and/or amplify Iref and to output an output current Iout. Specifically, the relation between Iout and Iref is determined in accordance with input bits arriving on busses 513, 513′, which gives DAC circuitry 502, 503 its digital-to-analog functionality. Essentially, in accordance with the values of the various M bits on bus 513, any number of output stages (i.e., transistors M1, M2) are tied together in parallel such that Iout can range from Iref to 2M*Iref. (Fractional values of Iref are also possible, as disclosed in the '969 patent, but such subtlety is ignored herein for simplicity). Although not shown in FIG. 1, the output stages can contain other structures, such as choke transistors and other transistors designed to ensure good current matching in the current mirror circuitry. However, as such other structures are explained in the above-incorporated '969 patent, they are not discussed further.
As shown in FIG. 1, the output current source 500 is coupled to an electrode EX on the IPG device 100, while the output current sink 501 is coupled to a different electrode EY on the IPG device. As explained in the above-incorporated '969 patent, an electrode will typically be hard-wired to both an output current source 500 and an output current sink 501, only one (or neither) of which is activated at a particular time to allow the electrode to selectively be used as either a source or sink (or as neither). Thus, for example, in FIG. 2A, four exemplary electrodes E1, E2, E3, and E4 are shown, each having their own dedicated source 500 and sink 501.
The source 500 and sink 501 hard-wired at each electrode are sometimes respectively referred to as PDACs and NDACs, reflecting the fact that the sources 500 are typically formed of P-type transistors while the sinks 501 are typically formed of N-type transistors. The use of transistors of these polarities is sensible given that the source is biased to a high voltage (V+), where P-type transistors are most logical, while the sink is biased to a low voltage (V−), where N-type transistors are most logical, as shown in FIG. 1. The substrate connection (not shown) for the transistors would typically be tied to the appropriate power supply, either V+ or V−, but could also be tied to the transistors' sources.
As shown in FIG. 2A, output current source 500 may be associated with electrode E2 (e.g., EX of FIG. 1) on the IPG at a particular point in time, while output current sink 501 may be associated with electrode E3 (e.g., EY of FIG. 1) at that time. At a later time, electrodes E2 and E3 could be switched such that E2 now operates as the sink, while E3 operates as the source, or new sources or sinks could be chosen, etc.
A consequence of this architecture is that, as mentioned, each electrode has its own dedicated source (i.e., PDAC) and sink (i.e., NDAC) circuitry, as shown in FIG. 2A. Consider an approach disclosed in the '969 patent, which is illustrated in FIG. 3. Shown is the dedicated output current source circuitry for a particular electrode (e.g., EX). Dedicated output current sink circuitry, similar to the output current source circuitry 500 but differing in polarity, would likewise be hardwired to the electrode EX, but is not shown for convenience. Also not shown for convenience is the presence of a coupling capacitor (see '969 patent, FIG. 3, element 203). As shown, the source is capable of outputting to the electrode a current Iout ranging from Iref to 127Iref in increments of Iref, depending on the status of the control bits (Bit<1:M>). Specifically, each bit, when selected, contributes 2(M−1) worth of current to the output current, Iout, through activation of pass transistors 530 in each of the M stages that comprise the output current source. For example, if a current of 53Iref is desired at Iout, bits Bit<1, 3, 5, 6> would be enabled (active low) to turn on transistors 5301, 5303, 5305, and 5306, which respectively contribute Iref, 4Iref, 16Iref and 32Iref, in sum, 53Iref. Although each stage is shown as having its own current source Iref, it would usually be the case that each stage taps into a singular reference current (not shown for convenience), which is preferred to ensure current uniformity across the stages.
However, this approach does not comprise an efficient use of space on the integrated circuit on which the output current source/sink circuitry is fabricated. In a typical SCS system implementation, the SCS device might contain 16 electrodes, E1 through E16. However, it is usually the case that only one PDAC (source) and one NDAC (sink) are active at one time. Or, more rarely, four or more PDACs (sources) or NDACs (sinks) might be active at one time. Even in the more extreme cases, it will be noted that the majority of the PDACs (source) and NDACs (sinks) are inactive. In other words, most of the time, most of the PDACs or NDACs dedicated to a particular electrode are not being utilized. When one considers that the PDACs or NDACs take up significant space on the integrated circuit (see FIG. 3), the provision of such redundancy for every electrode seems inefficient.
Another output current architecture is disclosed in the above-incorporated '227 patent, and in particular in FIG. 4A of the '227 patent, salient aspects of which are summarized in the present application in FIG. 2B. As shown in FIG. 2B, the architecture of the '227 patent also uses a plurality of current sources and sinks, and further uses a low impedance switching matrix that intervenes between the sources/sinks and the electrodes EX. Notice that each source/sink pair is hard-wired together at nodes 333, such that the switching matrix intervenes between the common nodes 333 and the electrodes. Of course, only one of the source or the sink in each pair is activated at one time, and thus point 333 in any pair will source or sink current at any particular time. Through appropriate control of the switching matrix, any of the nodes 333 may be connected to any of the electrodes EX at any time.
While generally a suitable architecture, the architecture of FIG. 2B suffers from drawbacks. For one, the FIG. 2B architecture puts additional resistance in the output path between the power supply in the DAC circuitry and the electrode. As explained in the above-incorporated '632 application, it is generally desired to minimize resistance between the power supply and the electrode. Thus, and referring to FIG. 4, which shows the architecture of FIG. 2B in further detail, it is desired that the resistance be minimized in the output path between the power supply V+ or V− and a given electrode EX. This is because any resistance in the output path will give rise to a voltage drop in the output path (the output path resistance times Iout) which is not otherwise useful in the context of the circuitry. But in the architecture of FIGS. 2B and 4, it can be seen that three elements are serially connected between the power supplies and the electrode: the current mirror, the bit select transistor, and the transistor in the low impedance switch matrix. Due to the additional resistances of these components, and the additional resistance of the switches in the switch matrix, power (i.e., the output path resistance times Iout) is wasted. In an implantable stimulator device, such unnecessary power loss is regrettable, because battery life in such devices is critical and beneficially made as long lasting as possible.
Moreover, the architecture of FIG. 2B is further inefficient from a layout perspective. Due to the common node between a given PDAC source and NDAC sink pair, only one DAC in each pair can be active at any time. Thus, and like the architecture of FIG. 2A, DAC circuitry is guaranteed to go unused at any particular time. More specifically, at least 50% of the DAC circuitry (possibly more) will go unused at any given time, which again is a wasteful use of layout on the integrated circuit.
In short, the implantable stimulator art, or more specifically the IPG or SCS system art, would be benefited by an architecture that allowed variable currents to be provided at a number of electrodes, but in a more efficient manner. Such solutions are provided herein.